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EM78862C
8-Bit Microcontroller
Product Specification
DOC. VERSION 2.1
ELAN MICROELECTRONICS CORP.
July 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 General Description............................................................................................................ 1 Features ............................................................................................................................... 1 2.1 3 4 5 6 CPU.............................................................................................................................. 1 2.2 LCD .............................................................................................................................. 2 Applications ........................................................................................................................ 2 3.1 Application Notes ......................................................................................................... 2 Pin Configurations.............................................................................................................. 3 4.1 Pin Description ............................................................................................................. 4 Functional Block Diagram.................................................................................................. 5 Functional Descriptions ..................................................................................................... 6 6.1 Operational Registers .................................................................................................. 6
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.1.18 R0 (Indirect Address Register) ...................................................................................... 6 R1 (TCC) ....................................................................................................................... 7 R2 (Program Counter) ................................................................................................... 7 R3 (Status Register) ...................................................................................................... 8 R4 (Register Bank Select Register) --- Page 0 ............................................................. 9 R5 (Program Page Select Register) --- Page 0............................................................. 9 R7 (Port7) --- Page 0 ..................................................................................................... 9 R8 (Port8) --- Page 0 ................................................................................................... 10 R9 (Port9) --- Page 0 ................................................................................................... 10 RA (Mode Control Register) --- Page 0 ....................................................................... 10 RA (LCD Address0~7) --- Page 1 ................................................................................ 12 RB (LCD Data Buffer) --- Page 1................................................................................. 12 RC (DATA RAM Data Buffer) ---Page 1..................................................................... 13 RD (DATA RAM Address0~7) --- Page 1..................................................................... 13 RE (KEYSCAN, LCD Control) --- Page 0 .................................................................... 13 RE (DATA RAM Address8 ~ 10) --- Page 1 ................................................................. 15 RF (INTERRUPT Flags*)............................................................................................. 15 R10 ~ R1F and R20 ~ R3F (General Purpose Registers) .......................................... 16 A (Accumulator, ACC).................................................................................................. 16 CONT (Control Register) ............................................................................................. 16 IOC5 (Port8 & Port9 Port Switch Register) --- Page 0 ................................................ 17 IOC7 (Port7 I/O Control Register) --- Page 0 .............................................................. 17 IOC8 (Port8 I/O Control Register) --- Page 0 .............................................................. 17 IOC9 (Port9 I/O Control Register) --- Page 0 .............................................................. 18 IOCA (CNT1 & CNT2 Clock Source and Scaling) --- Page 0...................................... 18 IOCA (PORT7 Pull-High Control Register) --- Page 1................................................. 19 IOCD (COUNTER 1 Data Buffer Register) --- Page 0................................................. 19 IOCE (COUNTER 2 Data Buffer Register) --- Page 0................................................. 19
* iii
6.2
Special Purpose Registers ......................................................................................... 16
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10
Product Specification (V2.1) 07.13.2005
Contents
6.2.11 IOCF (INTERRUPT Mask Register)............................................................................ 19
6.3 6.4 6.5 6.6 6.7 6.8 6.9
TCC/WDT Pre-Scale.................................................................................................. 20 I/O Ports ..................................................................................................................... 21 RESET ....................................................................................................................... 21 WAKE-UP .................................................................................................................. 23 Oscillator .................................................................................................................... 23 Interrupt...................................................................................................................... 24 LCD Driver ................................................................................................................. 25
6.10 Code Options ............................................................................................................. 27 7 8 9 10 11 6.11 Instruction Set ............................................................................................................ 27 Absolute Maximum Ratings............................................................................................. 30 DC Electrical Characteristics........................................................................................... 30 AC Electrical Characteristics........................................................................................... 31 Timing Diagram................................................................................................................. 31 Application Circuit ............................................................................................................ 32 11.1 Application with Crystal Mode .................................................................................... 32 12 11.2 Application with RC Mode .......................................................................................... 33 Bonding Coordinates Subsidiary .................................................................................... 34 12.1 Pad Configuration ...................................................................................................... 34 12.2 Pad Name and Coordinates Table ............................................................................. 35
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Product Specification (V2.1) 07.13.2005
Contents
Specification Revision History
Doc. Version 1.0 Initial version Revision Description Date Nov-16-2004
1.1
1.2
1.3
1.4 1.5 1.6 1.7
1.8
1.9
2.0 2.1
To match with EM78808: 1. Modified the LCD RAM address block diagram. 2. Renamed the SEGMENT pins. LCD Driver circuit Added one pin/pad for the voltage converter capacitor. Changed the LCD RAM address: 30h~3Fh 20h~2Fh, B0h~BFh A0h~Afh. Cancelled all functions of Port B and Port C. Added LCD segment from Seg32 to Seg47. Modified the Pin pad sequence. Added Port 7 (INT) wakeup function from sleep mode. DC Electrical Characteristic LCD Driver Voltage: 1. Ilcd=0A , 4.5V 1.5VDD 2. Ilcd=-150A , 4.4V 1.47VDD Modified the VDD range: 2.2 ~ 5.5V 2.2~3.6V Modified the pin pad sequence Cancelled the IOC REGISTER: IOC5 PAGE 1 ( LCD bias control ) Added Counters 1 & 2 Wake-up function Modified the pin pad sequence Application notes Look-up table issue TBL instruction action R2+1, R2+A Deleted the information on IOC6 Register Added Application Note on the proper use of the Reset register Provided separate registers info for ICE-808 & EM788862C Revised the Operation Register RE real chip initial value 1. RE Page 0 Bit 4 fixed flexible 2. RE Page 1 Bit 7...0 1 Added Bonding Coordinates Subsidiary Modified the DC Electrical Characteristics 1. Modified the VOH, VOL condition value. 2. Added LCD enable/disable of IDLE mode current value.
Nov-23-2004
Dec-20-2004
Dec-21-2004 Dec-23-2004 Jan-12-2005 Jan-14-2005 Feb-04-2005
Mar-02-2005
Mar-08-2005 Apr-14-2005 Jul-13-2005
Product Specification (V2.1) 07.13.2005
v
EM78862C
8-Bit RISC Type Microprocessor
1
General Description
The EM78862C is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. Integrated into the single chip are built-in watchdog (WDT), RAM, ROM, programmable real-time clock/counter, internal interrupt, power-down mode, LCD driver, and bi-directional I/O. The EM78862C provides a single chip solution for scientific calculator design applications.
2
Features
2.1 CPU
Operating voltage range: 2.2V ~ 3.6V 16K x 13 on-chip ROM 1.25K x 8 on-chip RAM 144 byte working register Up to 24 bi-directional I/O ports (16 shared with LCD segment pins) 8 level stack for subroutine nesting 8-bit real time clock/counter (TCC) can be configured as interrupt sources with prescaler Two sets of 8 bit counters are set as interrupt sources with prescaler Programmable free running on-chip watchdog timer Four modes (internal PLL clock 3.579MHz)
* * * *
SLEEP Mode:CPU and 3.579MHz clock turn off, 32.768kHz clock turn off IDLE Mode:CPU and 3.579MHz clock turn off, 32.768kHz clock turn on GREEN Mode: 3.579MHz clock turn off, CPU and 32.768kHz clock turn on
NORMAL Mode: 3.579MHz clock turn on, CPU and 32.768kHz clock turn on Input port wake up function Six interrupt sources: three internal, three external 1. TCIF for TCC timer overflow interrupt 2. CNT1 for COUNTER 1 overflow interrupt 3. CNT2 for COUNTER 2 overflow interrupt
* Internal:
* External:
1. INT 0 for Port 70, Port 71, Port 72, or Port 73, has a falling edge trigger interrupt 2. INT 1 for Port 74, Port 75, or Port 76, has a falling edge trigger interrupt 3. INT 3 for Port 77 has a rising edge or falling edge trigger (by CONT register) interrupt 67-pin die chip (EM78862CH) Port key scan function Clock frequency 32.768kHz or RC mode
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
*1
EM78862C
8-Bit RISC Type Microprocessor
2.2 LCD
LCD operation voltage: 4.5 V ( VDD must be fixed at 3V ) Common driver pins: 16 Segment driver pins: 32 1/4 bias 1/16 duty
3
Applications
Data Bank Message display box Scientific calculator
3.1 Application Notes
In switching the main clock (from high frequency to low frequency or vice versa), or waking up from idle mode, 6 ~ 8 delay instructions (NOP) must be added. Avoid directly switching to Idle mode or Sleep mode from Normal mode. You must initially switch to Green mode, and then to Idle mode or Sleep mode. Under DATA RAM least address (A0~A7), when "INC" instruction is in use and overflow occurs, the middle address will automatically be incremented. If "DEC" instruction and least address from 0x000xFF is used, the middle address cannot and will not be automatically decremented. The Look-up table instruction can only change the program counter's Bit 7 ~ Bit 0 at a time and only 256 address can be searched on one occasion. If each 256 address is called as "zone" and each program page contains 1024 address, then each page contains four zones. When two zones overlap within a table, a bug will occur during address search. So you must examine the *.LST file after each compilation. The *.LST file will jot down the information, instruction address, etc., as well as the error messages if bug is found. During a reset, the values of the registers in the target chip (EM78862C) and that of ICE-808 may differ from each other. As the 808 ROMless chip of ICE is used to develop a program for EM78862C, its reset (initial) values cannot be repeated as reset values for the target chip. Otherwise, error may occur. The register reset values for the target chip should be those described in the EM78862C specification, not those from ICE-808. Applicable MASK, OTP, and ICE
MASK EM78862C OTP EM78P808 ICE ICE 808
2*
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
4
Pin Configurations
COM 10 COM 12 COM 13 COM 14 COM 11 COM 15 SEG 32 SEG 33 SEG 34 SEG 35 SEG 36 SEG 37 47 SEG 38 46 45 44 43 42 41 40 39 SEG 39 SEG 40 SEG 41 SEG 42 SEG 43 SEG 44 SEG 45 SEG 46 SEG 47 38 37 COM 1 COM 3 COM 4 COM 5 COM 6 COM 7 COM 2 COM 8 60 COM 9 59
67 COM 0 C45 C15 C1A C1B RESETB TEST OSCO OSCI GND PLLC VDD P77/INT2 P76/INT1 P75/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
66
65
64
63
62
61
58
57
56
55
54
53
52
51
50
49
48
EM78862C
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P74/INT1
P73/INT0
P97/SEG79
P96/SEG78
P95/SEG77
P94/SEG76
P93/SEG75
P92/SEG74
P91/SEG73
P90/SEG72
P87/SEG71
P86/SEG70
P85/SEG69
P84/SEG68
P83/SEG67
P82/SEG66
P81/SEG65
Fig. 1 EM78862C Pin Configuration for Die Form
P80/SEG64
P72/INT0
P71/INT0
P70/INT0
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
*3
EM78862C
8-Bit RISC Type Microprocessor
4.1 Pin Description
Pin Name VDD GND OSCI OSCO COM0 ~ COM15 SEG32 ~ SEG47 SEG64 ~ SEG79 PLLC Pin # 12 10 9 8 1 53~67 37 ~ 52 21 ~ 36 11 I/O Type Power Power I O O O I Description Digital power and analog power Digital and analog ground Input pin for 32.768 kHz oscillatoror installing a resistor for RC mode Output pin for 32.768 KHz oscillator Common driver pins of LCD driver Segment driver pins of LCD driver Phase loop lock capacitor. Connect a capacitor 0.01 to 0.047 with GND Interrupt sources which have the same interrupt flag. Any pin from PORT70 to PORT73 has a falling edge signal, it will generate an interruption. Interrupt sources which have the same interrupt flag. Any pin from PORT74 to PORT76 has a falling edge signal, it will generate an interruption. Interrupt source. Once PORT77 receives a falling edge or rising edge signal (controlled by CONT register), it will generate an interruption. PORT7 (INPUT or OUTPUT port per bit) Internal Pull-high function Key scan function PORT8 (INPUT or OUTPUT port per bit) Shared with LCD segment signals PORT9 INPUT or OUTPUT port per bit And is shared with Segment signal Capacitor C1 (1F) connector pin for Voltage converter . Capacitor C1 (1F) connector pin for voltage converter . Connect each with a capacitor (1F) to GND for voltage converter pin. Test pin during Test mode only. Normally LOW System reset pin ( LOW ACTIVE )
INT0
17 ~ 20
I
INT1
14 ~ 16
I
INT2
13
I
P7.0 ~ P7.7 P8.0 ~ P8.7 P9.0 ~ P9.7 C1A C1B C15 , C45 TEST RESETB
13 ~ 20 29 ~ 36 21 ~ 28 4 5 3,2 7 6
I/O I/O I/O I I I I I
4*
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
5
Functional Block Diagram
Fig. 2a System Overview Block Diagram
Fig. 2b System Functional Block Diagram
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
*5
EM78862C
8-Bit RISC Type Microprocessor
6
Functional Descriptions
6.1 Operational Registers
ADDRESS REGISTER (PAGE0) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F RE(Key scan , LCD control) RF(Interrupt flag) R7(PORT 7) R8(PORT 8) R9(PORT 9) RA(CLOCK,WDT) RA(LCD_A0~7) RB (LCD_ D0~7) RC(RAM_D0~7) RD(RAM_A0~7) RE( RAM_A8~10) IOCD(COUNTER1 PRESET) IOCE(COUNTER2 PRESET) IOCF(Interrupt control) IOC7 (PORT7 IO control) IOC8 (PORT8 IO control) IOC9 (PORT9 IO control IOCA(COUNTER1,2, prescaler and source) IOCA(PORT7 pull high) R0 R1(TCC buffer) R2(PC) R3(STATUS) R4(RSR, BANK SELECT) R5(Program ROM page) IOC5(P8S,P9S) R3(7) R3(5,6) REGISTER (PAGE1) CONTROL REGISTER (PAGE0) CONTROL REGISTER (PAGE1)
10 : 1F 20 : R4(7,6) 3F
16 byte COMMON REGISTER LCD RAM(32Sx16C) BANK0 , BANK1, BANK2 ,BANK3 32X8 32X8 32X8 32X8 COMMON REGISTER RA PAGE1 => address RB PAGE1 => data DATA RAM(1.25KB=0~4FFh) RD PAGE1 => address7..0 RE PAGE1 => address10..8 RC PAGE1 => data
Fig. 3 Data Memory Configuration
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example:
MOV MOV MOV MOV
A,@0x20 0x04,A A,@0xAA 0x00,A
;Store an address at R4 for indirect addressing
;Write data 0xAA to R20 at Bank0 through R0
6*
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.1.2 R1 (TCC)
TCC data buffer. Increased by 16.38kHz, RC/2 or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
6.1.3 R2 (Program Counter)
The structure is depicted in Fig. 4 below. Generates 16K x 13 on-chip PROGRAM ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push it into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0'.' "ADD R2,A" allows a relative address to be added to the current PC, and contents of the ninth and tenth bits are cleared to "0'.' "TBL" allows a relative address to be added to the current PC, and contents of the ninth and tenth bits do not change. The most significant bit (A10~A13) will be loaded with the content of bit PS0 ~ PS3 in the status register (R5) upon execution of a "JMP',' "CALL',' "ADD R2,A,', or "MOV R2,A'' instruction. If an interrupt triggers, the PROGRAM ROM will jump to address 0008H at Page 0. The CPU will automatically store the ACC, R3 status and R5 PAGE. It will be restored after instruction RETI is executed.
R5(PAGE)
CALL and INTERRUPT A9 A8 PAGE0 PAGE1 PAGE2 A7~A0 0000~03FF 0400~07FF 0800~0BFF RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 Store ACC,R3,R5(PAG) Restore
PC
A13 A12 A11 A10 0000 0001 0010
1110 1111
PAGE14 PAGE15
3800~3BFF 3C00~3FFF
Fig. 4 Program Counter Organization
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
*7
EM78862C
8-Bit RISC Type Microprocessor
6.1.4 R3 (Status Register)
Bit 7 PAGE Bit 6 IOCP1S Bit 5 IOCPAGE Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 0 (C): Carry flag Bit 1 (DC): Auxiliary carry flag Bit 2 (Z): Zero flag Bit 3 (P): Power down bit. Set to 1 during power on or by "WDTC" command and reset to 0 by "SLEP" command. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up. Reset to 0 by WDT timeout.
Event WDT wake-up from sleep mode WDT time out (not sleep mode) RESET wake up from sleep Power up Low pulse on RESET pin T 0 0 1 1 X P 0 1 0 1 X X =Don't care Remark
Bit 5 (IOCPAGE): Change IOC5 ~ IOCE to another page, 0/1 Page0/Page1 or 2 (determined by R3 Bit 6) Bit 6 (IOCP1S): Change IOC PAGE1 and PAGE2 to another option register 0/1 page1/page2 (Refer to Fig. 3, Data Memory Configuration for the control register Configuration details.)
Bit 6 (IOCP1S) X 0 1 Bit 5 (IOCPAGE) 0 1 1 Page Select PAGE 0 PAGE 1 PAGE 2 Remark X =Don't care
Bit 7 (PAGE):
Change RA ~ RE to another page 0/1 page0/page1
(Refer to Fig. 3, Data Memory Configuration for the control register Configuration details.)
8*
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.1.5 R4 (Register Bank Select Register) --- Page 0
Bit 7 RBK1 Bit 6 RBK0 Bit 5 RSR5 Bit 4 RSR4 Bit 3 RSR3 Bit 2 RSR2 Bit 1 RSR1 Bit 0 RSR0
Bit 0 ~ Bit 5 (RSR0 ~ RSR5): Indirect addressing for common Registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in indirect addressing mode. Bit 6 ~ Bit 7 (RBK0 ~ RBK1): Bank selection bits for common Registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks of 32 registers (R20 to R3F) each. (Refer to Fig. 3, Data Memory Configuration for the control register Configuration details.)
6.1.6 R5 (Program Page Select Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PS3 Bit 2 PS2 Bit 1 PS1 Bit 0 PS0
Bit 0 ~ 3 (PS0 ~ PS3): Page select bits as shown below:
PS3 0 0 0 1 1 PS2 0 0 0 :: 1 1 1 1 0 1 PS1 0 0 1 PS0 0 1 0 Program Memory Page (Address) Page 0 Page 1 Page 2 :: Page 14 Page 15
You can use PAGE instruction to change and maintain program page. Otherwise, use far jump (FJMP) or far call (FCALL) MACRO instructions to program user's code. ELAN's complier supports program page maintenance and can change your program by inserting the appropriate instructions within the program. Bit 4 ~ 7: Not used
6.1.7 R7 (Port 7) --- Page 0
Bit 7 P77 Bit 6 P76 Bit 5 P75 Bit 4 P74 Bit 3 P73 Bit 2 P72 Bit 1 P71 Bit 0 P70
Bit 0 ~ Bit 7 (P70 ~ P77): 8-bit PORT7 (0 ~ 7) I/O data register You can use IOC7 Page 0 register to define each bit as input or output.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
*9
EM78862C
8-Bit RISC Type Microprocessor
6.1.8 R8 (Port8) --- Page 0
Bit 7 P87 Bit 6 P86 Bit 5 P85 Bit 4 P84 Bit 3 P83 Bit 2 P82 Bit 1 P81 Bit 0 P80
Bit 0 ~ Bit 7 (P80 ~ P87): 8-bit PORT8 (0 ~ 7) I/O data register You can use IOC8 Page 0 register to define each bit as input or output.
6.1.9 R9 (Port9) --- Page 0
Bit 7 P97 Bit 6 P96 Bit 5 P95 Bit 4 P94 Bit 3 P93 Bit 2 P92 Bit 1 P91 Bit 0 P90
Bit 0 ~ Bit 7 (P90 ~ P97): 8-bit PORT9 (0 ~ 7) I/O data register You can use IOC9 Page 0 register to define each bit as input or output.
6.1.10 RA (Mode Control Register) --- Page 0
Bit 7 IDLE Bit 6 PLLEN Bit 5 CLK1 Bit 4 CLK0 Bit 3 Bit 2 Bit 1 Bit 0 WDTEN
Bit 0 (WDTEN): Watch dog control register 0/1 disable/enable You can use WDTC instruction to clear watch dog timer. The timer's clock source is 32.768k/2 Hz. If the prescaler is assigned to TCC, the watchdog timer will time out by (1/32768) * 2 * 256 = 15.616ms. If assigned to WDT, the time out time will be longer than 15.616ms depending on the prescaler ratio. Bit 1 ~ Bit 3: Not used
Bit 4 ~ Bit 5 (CLK0 ~ CLK1): Main clock = 3.579Mhz, CLK0 ~ CLK1 are set to `1'. Bit 6 (PLLEN): PLL enable control bit 0/1 disable/enable This is the CPU mode control register. If PLL is enabled, CPU will operate under Normal mode (high frequency, main clock). Otherwise, it will run under Green mode (low frequency, 32.768kHz). The relation between 32.768K and 3.579M crystal is explained in the following figure.
10 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
Fosc OSCI OSCO 32.768kHz RC/Crystal OSC
0 Fsystem 1
PLL
FPLL
"OSC_SEL "bit PLL_EN of code option
Fig. 5 The Relation between 32.768KHz and 3.579MHz Bit 7 (IDLE): Power saving mode control register When PLL is disabled, you can set this bit with SLEP instruction to define SLEEP/IDLE mode selection, i.e., 0/1 SLEEP mode/IDLE mode. This bit determines which mode will be set for SLEP instruction.
Wakeup Signal SLEEP Mode IDLE Mode GREEN Mode NORMAL Mode
RA(7,6)=(0,0) + SLEP TCC Time-Out Counter 1 Time-Out Counter 2 Time-Out Port7.0 ~ 7.7 (INT0~2) WDT Time-Out X
X
X
RESET RESET
RA(7,6)=(1,0) + SLEP Wake-up + Interrupt + Next instruction Wake-up + Interrupt + Next instruction Wake-up + Interrupt + Next instruction Wake-up + Interrupt + Next instruction Wake-up + Next instruction
RA(7,6)=(x,0) no SLEP Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) RESET
RA(7,6)=(x,1) no SLEP Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) RESET
NOTE 1. 2. 3. PORT 70 ~ PORT 73's wake-up function is controlled by IOCF Bit 3 and ENI instruction. They are triggered by a falling edge. PORT 74 ~ PORT 76's wake-up function is controlled by IOCF Bit 4 and ENI instruction. They are triggered by a falling edge. PORT 77's wake-up function is controlled by IOCF Bit 5 and ENI instruction. It is triggered by a falling edge or a rising edge (controlled by CONT register).
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 11
EM78862C
8-Bit RISC Type Microprocessor
6.1.11 RA (LCD Address0~7) --- Page 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD_A7
LCD_A6
LCD_A5
LCD_A4
LCD_A3
LCD_A2
LCD_A1
LCD_A0
Bit 0 ~ Bit 7 (LCD_A0 ~ LCD_A7): LCD address for LCD RAM reading or writing The LCD RAM corresponds to the COMMON and SEGMENT signals as shown in the following table:
COM15 ~COM8 COM7 ~ COM0 SEGMENT
Address 80H : Address 9FH Address A0H Address A1H : Address AEH Address AFH Address B0H : Address BFH Address C0H Address C1H : Address CEH Address CFH Address D0H : Address FFH
Address 00H : Address 1FH Address 20H Address 21H : Address 2EH Address 2FH Address 30H : Address 3FH Address 40H Address 41H : Address 4EH Address 4FH Address 50H : Address 7FH
Dummy : Dummy SEG 32 SEG 33 : SEG 46 SEG 47 Dummy : Dummy SEG 64 SEG 67 : SEG78 SEG79 Dummy : Dummy
6.1.12 RB (LCD Data Buffer) --- Page 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
Bit 0 ~ Bit 7 (LCD_D0 ~ LCD_D7): LCD data buffer for LCD RAM reading or writing Example. MOV MOV MOV MOV MOV MOV A,@0 R9_PAGE1,A RA_PAGE1,A A,@0XAA RB_PAGE1,A A,RB_PAGE1
;Address ;Write data 0xAA to LCD RAM ;Read data from LCD RAM
12 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.1.13
Bit 7
RC (DATA RAM Data Buffer) ---Page 1
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RAM_D7
RAM_D6
RAM_D5
RAM_D4
RAM_D3
RAM_D2
RAM_D1
RAM_D0
Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM data buffer for RAM reading or writing. Example: MOV A , @1 MOV RD_PAGE1 , A MOV A , @0 MOV RE_PAGE1 , A MOV A , @0x55 MOV RC_PAGE1 , A MOV A , RC_PAGE1
;Write data 0x55 to DATA RAM which address is "0001" ;Read data
6.1.14
Bit 7
RD (DATA RAM Address0~7) --- Page 1
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RAM_A7
RAM_A6
RAM_A5
RAM_A4
RAM_A3
RAM_A2
RAM_A1
RAM_A0
Bit 0 ~ Bit 7(RAM_A0~RAM_A7): Data RAM address for RAM reading or writing
6.1.15
Bit 7
RE (KEYSCAN, LCD Control) --- Page 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
-
-
K_SCAN
LCD_C1
LCD_C0
LCD_M1
LCD_M0
Bit 0 ~ Bit 1 (LCDM0~LCDM1):
Set to "0" for 1/16 duty, 1/4 bias.
Bit 2 ~ Bit 3 (LCD_C0~LCD_C1): LCD operation function definition.
LCD_C1, LCD_C0 LCD Operation
0,0 0,1 1,0 1,1
Disable Blanking Reserved LCD enable
Bit 4 (K_SCAN): Key scan function enable control bit. 0/1 disable/enable Once you enable this bit, all of the LCD signal will have a low pulse during a common or segment period. This pulse has a 30s width. Use the following procedures to implement the key scans function: a) b) c) d) Set Port 7 as input port Set IOCA Page 1 Port 7 to pull high Enable scan key signal Once a key is pressed, set RA (6) = 1, and switch to normal mode e) Blank LCD. Disable scan key signal
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 13
EM78862C
8-Bit RISC Type Microprocessor f) Set P9SL = 0, P9SH = 0. Port9 sends probe signal to Port7 and read Port7 to get the key. Note that a probe signal instruction delay will occur before the next instruction is performed.
g) Set P9SH = 1, P9SL = 1. Define Port9 as LCD signal and enable LCD.
KEY5 P93 P92 P91 P90
KEY1 KEY2 KEY3 KEY4
P73
P72
P71
P70
Fig. 6 Scan Key Circuit
Com 2
VDD V1 V2 V3 VLCD GND VDD V1 V2 V3 VLCD GND
Seg
30
Fig. 7 Key Scan Waveform
14 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
NOTE 1. The controller can drive the LCD directly. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins, and LCD operating voltage converter capacitor pins. LCD voltage converter pins C1A & C1B should be connected with a C1 (1uF) capacitor. C14 & C45 need to be connected with 1uF capacitors to the ground. The number of common and frame frequency are determined by LCD mode Register RE PAGE0 Bit 0~ Bit 1. LCD driver can be regulated into different levels of driving mode (refer to Section 6.2.4, "IOC6 PAGE2" register). The basic structure contains a timing control which uses the basic frequency 32.768kHz to generate the proper timing for display access. RE PAGE0 register is a command register for LCD driver and display. The LCD display (disable, enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving duty is decided by RE PAGE Bit 0 ~ Bit 1. LCD display data is stored in LCD RAM which address and data access are controlled by registers RA PAGE1 and RB PAGE1.
2. 3. 4.
Bits 5 ~ Bit 7: Not used
6.1.16 RE (DATA RAM Address8 ~ 10) --- Page 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
-
-
-
-
RAM_A10 RAM_A9
RAM_A8
Bit 0 ~ Bit 2 (RAM_A8~RAM_A10): Data RAM address (Address8 to Address10) for RAM reading (can be addressed from 0h to 4FFh maximum). Bit 3 ~ Bit 7: Not used.
6.1.17 RF (INTERRUPT Flags*)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
-
INT2
INT1
INT0
CNT2
CNT1
TCIF
* "1" = interrupt request;
"0" = non-interrupt
Bit 0 (TCIF): TCC timer overflow interrupt flag When TCC timer overflows, interrupt is set. Bit 1 (CNT1): Counter1 timer overflow interrupt flag When Counter1 timer overflows, interrupt is set. Bit 2 (CNT2): Counter2 timer overflow interrupt flag When Counter2 timer overflows, interrupt is set. Bit 3 (INT0): External INT0 pin interrupt flag When PORT70, PORT71, PORT72, or PORT73 encounters a falling edge trigger signal, CPU sets this bit to interrupt.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 15
EM78862C
8-Bit RISC Type Microprocessor Bit 4 (INT1): External INT1 pin interrupt flag When PORT74, PORT75, or PORT76 encounters a falling edge trigger signal, CPU sets this bit to interrupt. Bit 5 (INT2): External INT2 pin interrupt flag When PORT77 encounters a falling s this bit to interrupt. Bits 6 ~ 7: Not used.
6.1.18 R10 ~ R1F and R20 ~ R3F (General Purpose Registers)
R10 ~ R1F & R20 ~ R3F (Banks 0~3) are general-purpose registers
6.2 Special Purpose Registers
6.2.1 A (Accumulator, ACC)
Internal data transfer, or instruction operand holding. This is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INT_EDG E
INT
TS
-
PAB
PSR2
PSR1
PSR0
Bit 0 ~ Bit 2 (PSR0~PSR2): TCC/WDT pre-scale bits
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 3 (PAB): Prescaler assigned bit 0/1 TCC/WDT Bit 4: Not used
Bit 5 (TS): TCC signal source 0 Instruction clock 1 16.384kHz or RC/2 Instruction clock = MCU Clock/2. Refer to RA Bit 4 ~ Bit 6 Page 0 for PLL (Section 6.1.10) and Main Clock selection (Section 6.3, Fig.8).
16 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor Bit 6 (INT): INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7 (INT_EDGE): interrupt edge type of P77 0 P77's interrupt source is a rising edge and falling edge signal. 1 P77's interrupt source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW).
6.2.3 IOC5 (Port8 & Port9 Port Switch Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
-
-
-
P9SH
P9SL
P8SH
P8SL
Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for share pins SEGnn/P8n pins 0 select normal P80 ~ P83 for low nibble PORT8 1 select SEG64 ~ SEG67 output for LCD SEGMENT output Bit 1 (P8SH): Switch high nibble I/O PORT8 or LCD segment output for share pins SEGnn/P8n 0 select normal P84 ~ P87 for high nibble PORT8 1 select SEG68 ~ SEG71 output for LCD SEGMENT output Bit 2 (P9SL): Switch low nibble I/O PORT9 or LCD segment output for share pins SEGnn/P9n pins 0 select normal P90 ~ P93 for low nibble PORT9 1 select SEG72 ~ SEG75 output for LCD SEGMENT output Bit 3 (P9SH): Switch high nibble I/O PORT9 or LCD segment output for share pins SEGnn/P9n pins 0 select normal P94 ~ P97 for high nibble PORT9 1 select SEG76 ~ SEG79 output for LCD SEGMENT output. Bits 4 ~ 7: Not used
6.2.4 IOC7 (Port7 I/O Control Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC77
IOC76
IOC75
IOC74
IOC73
IOC72
IOC71
IOC70
Bit 0 ~ Bit 7(IOC70 ~ IOC77): PORT7(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin as input (high impedance)
6.2.5 IOC8 (Port8 I/O Control Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC87
IOC86
IOC85
IOC84
IOC83
IOC82
IOC81
IOC80
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 17
EM78862C
8-Bit RISC Type Microprocessor Bit 0 ~ Bit 7(IOC80 ~ IOC87): PORT8(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin as input (high impedance)
6.2.6 IOC9 (Port9 I/O Control Register) --- Page 0
Bit 7 IOC97 Bit 6 IOC96 Bit 5 IOC95 Bit 4 IOC94 Bit 3 IOC93 Bit 2 IOC92 Bit 1 IOC91 Bit 0 IOC90
Bit 0 ~ Bit 7(IOC90 ~ IOC97): PORT9 (0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance (input)
6.2.7 IOCA (CNT1 & CNT2 Clock Source and Scaling) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CNT2S
C2P2
C2P1
C2P0
CNT1S
C1P2
C1P1
C1P0
Bit 0 ~ Bit 2 (C1P0 ~ C1P2): Counter1 scaling
C1P2 C1P1 C1P0 Counter 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (CNT1S):
Counter 1 clock source 0/1 (16.384kHz or RC/2) / instruction clock
Bit 4 ~ Bit 6 (C2P0 ~ C2P2): Counter2 scaling
C2P2 C2P1 C2P0 Counter 2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 7 (CNT2S):
Counter 2 clock source 0/1 (16.384kHz or RC/2) / instruction clock
18 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.2.8 IOCA (PORT 7 Pull-High Control Register) --- Page 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PH77
PH76
PH75
PH74
PH73
PH72
PH71
PH70
Bit 0 ~ Bit 7 (PH70 ~ PH77): PORT7 (0~7) pull high control register 0 disable pull high function 1 enable pull high function
6.2.9 IOCD (COUNTER 1 Data Buffer Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CNT1_D7 CNT1_D6 CNT1_D5 CNT1_D4 CNT1_D3 CNT1_D2 CNT1_D1 CNT1_D0
Bit 0 ~ Bit 7 (CNT1_D0~CNT1_D7): Counter1's data buffer User can read and write to this buffer. Counter1 is an 8-bit up-counter with 8-bit prescaler that uses IOCD to preset and read the counter (write = preset). After an interruption, it will reload the preset value. Examples: Write: IOW 0x0D ;write the data at accumulator to Counter1 ;(preset) Read: IOR 0x0D ;read IOCD data and write to accumulator
6.2.10 IOCE (COUNTER 2 Data Buffer Register) --- Page 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CNT2_D7 CNT2_D6 CNT2_D5 CNT2_D4 CNT2_D3 CNT2_D2 CNT2_D1 CNT2_D0
Bit 0 ~ Bit 7 (CNT2_D0 ~ CNT2_D7): Counter2's data buffer User can read and write this buffer. Counter 2 is an 8-bit up-counter with 8-bit pre-scale that uses IOCE to preset and read the counter (write = preset). After an interruption, it will reload the preset value. Examples: Write: IOW 0x0E ;write the data at accumulator to Counter2 (preset) Read: IOR 0x0E ;read IOCE data and write to accumulator
6.2.11 IOCF (INTERRUPT Mask Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
-
INT2
INT1
INT0
CNT2
CNT1
TCIF
Bit 0 ~ Bit 5: Interrupt enable bits 0/1 disable interrupt/enable interrupt Bit 6 ~ Bit 7: Not used
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 19
EM78862C
8-Bit RISC Type Microprocessor
6.3 TCC/WDT Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available only to either the TCC or WDT at a time. An 8-bit counter is made available for TCC or WDT as determined by the status of Bit 3 (PAB) of CONT register. The prescaler ratio is described in Section 6.2.2, CONT (Control Register). The TCC/WDT circuit diagram is shown in Fig. 10 below. Both TCC and prescaler are cleared by instructions. The prescaler will be cleared by the WDTC and SLEP instructions when running under WDT mode. However, the prescaler cannot be cleared by SLEP instruction when running under TCC mode.
NOTE CONT is a readable and writable register.
CLK = Fosc/2
0
16.38kHz or RC/2
Data Bus
1 SYNC 2 Cycles 1 0
TCC(R1)
OSCSEL
0
TS
PAB
TCC Overflow Interrupt
W DT
1
8-BIT Counter
PAB W DTE
8-to-1 MUX
0 1
PSR0~PSR2
MUX
PAB
W DT Tim eout
Fig. 8 TCC WDT Block Diagram
20 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.4 I/O Ports
The I/O registers (Ports 7, 8, and 9), are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by software. Furthermore, each I/O pin can be defined as "input" or "output" pin by the I/O control registers (IOC7 ~ IOC9). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits are shown in Fig. 9 below.
Fig. 9 Ports 7, 8, & 9 I/O Port and I/O Control Register Circuit
6.5 RESET
RESET will occur during any of the following conditions: Power on reset WDT timeout (if WDT is enabled during SLEEP, GREEN, or NORMAL mode) RESET pin pull low Once a RESET occurs, the following functions are performed: The oscillator will continue running and the Program Counter (R2) is set to all "0" All I/O port pins are configured to input mode (high-impedance state) The TCC/Watchdog timer and prescaler are cleared and Watchdog timer is disabled When power is switched on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared The bits of the CONT register are set to all "1"
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 21
EM78862C
8-Bit RISC Type Microprocessor For the other registers (Bit 7 ~ Bit 0), refer to the following table: ICE-808 Registers
Address R Register Page0 R Register Page1 IOC Register Page0 IOC Register Page1 IOC Register Page2
4 5 6 7 8 9 A B C D E F
00xxxxxx xxxx0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000xx0 xxxxxxxx xxxxxxxx 00000000 00000000 00000000
00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00xxxxxx -
11100000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 00000000 00000000 00000000
00000000 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 00000000 -
xxxxxxxx 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000
EM78862C Registers
Address R Register Page0 R Register Page1 IOC Register Page0 IOC Register Page1 IOC Register Page2
4 5 6 7 8 9 A B C D E F
00xxxxxx 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00110110 00000000 00000000 00110000 10000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10000xxx -
11100000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 00000000 00000000 00000000
11000000 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 00000000 -
00000000 00000000 00000000 -
Shaded bits are circuit fixed value
22 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.6 WAKE-UP
The WAKE-UP signals are as follows:
Sleep Mode Wake-Up Signal RA(7,6)=(0,0) + SLEP Idle Mode RA(7,6)=(1,0) + SLEP Green Mode RA(7,6)=(x,0) No SLEP Normal Mode RA(7,6)=(x,1) No SLEP
TCC time out IOCF Bit0=1 Counter 1 time out IOCF Bit1=1 Counter 2 time out IOCF Bit2=1 INT0 pin(P70~3) IOCF Bit3=1 INT1 pin(P74~6) IOCF Bit4=1 INT2 pin(P77) IOCF Bit5=1 WDT time out
X X X RESET RESET RESET RESET X = No function
Wake-up+ Interrupt + Next instruction Wake-up+ Interrupt + Next instruction Wake-up+ Interrupt + Next instruction Wake-up+ Interrupt + Next instruction Wake-up+ Interrupt + Next instruction Wake-up+ Interrupt + Next instruction Wake-up+ next instruction
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt RESET
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt RESET
6.7 Oscillator
The oscillator system is used to generate the device clock. The oscillator system is composed of an RC or crystal oscillator and a PLL oscillator as illustrated below.
Fosc OSCI OSCO
32.768khz RC/Crystal OSC
0 Fsystem 1
PLL
FPLL
"OSC_SEL "bit of code option
PLL_EN
Fig. 10 Oscillator and PLL Function Block
NOTE 1. 2. Under RC oscillator mode, the pull-up resistor that connects to OSCI pin and OSC0 pin should be floating. Under 32.768kHz crystal oscillator mode, the crystal is connected between OSCI pin and OSCO pin. A 20~30pF capacitor should be connected between each of the pins and ground.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 23
EM78862C
8-Bit RISC Type Microprocessor
6.8 Interrupt
The EM78862C IC has two types of internal interrupts which are falling edge triggered: TCC timer overflow interrupt (internal) Two 8-bit counters overflow interrupt If these interrupt sources change signal from high to low, the RF register will generate '1' flag to the corresponding register if IOCF register is enabled. RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (if enabled) is generated, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. Four external interrupt pins, i.e., INT0, INT1, INT2, & INT3, and three internal interrupts are available: External interrupt signals (INT0, INT1 and INT2) are from Port7 Bit 0 to Bit 7. If IOCF is enabled, then these signals will activate interrupt. Otherwise, these signals will be treated as general input data. Internal signals include TCC, CNT1, and CNT2. After a reset, the next instruction will be fetched from Address 000H and the hardware interrupt is 008H. After timeout, TCC will go to Address 008H when in GREEN mode or NORMAL mode. When in IDLE mode, TCC will go to Address 008H run interrupt service. After RETI instruction jump to the next instruction after "SLEP" instruction. These two conditions will set a RF flag. The interrupt flag bit must be cleared in software before leaving the interrupt service routine in order to prevent and avoid recursive interrupts.
NOTE It is very important to save ACC, R3, and R5 when processing an interrupt as illustrated below:
24 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E DISI MOV SWAP SWAPA MOV MOV MOV : : MOV MOV SWAPA MOV SWAPA RETI ;Disable interrupt ;Save ACC ;Save R3 status ;Save ROM page register
A_BUFFER, A A_BUFFER 0x03 R3_BUFFER, A A, 0x05 R5_BUFFER, A
: : : : : :
A, R5_BUFFER 0X05,A R3_BUFFER 0X03,A A_BUFFER
;Return R5 ;Return R3 ;Return ACC
6.9 LCD Driver
The IC can drive LCD directly and has 32 segments and 16 commons that can drive a total of 32*16 dots. LCD block is made up of LCD driver; display RAM, segment output pins, common output pins, and LCD operating power supply pins. The basic structure (as illustrated in Figs 11, 12, & 13) contains a timing control which uses the basic frequency 32.768kHz or RC to generate the proper timing for display access. RE register is a command register for LCD driver. The LCD display (disable, enable, & blanking) is controlled by LCD_C and the driving duty and bias is decided by LCD_M. The display data is stored in data RAM which address and data access are controlled by registers RA Page1 and RB Page1.
3 2 .7 6 8 k H z C rys ta l o r R C R A P a g e 1 (A d d re s s ) R B P a g e 1 (D a ta ) L C D T im in g C o n tro l LC D R AM
R E P age 0 LC D _C 1~0 LC D _M 1~0
L C D 1 /1 6 D u ty C o n tro l
D is p la y D a ta C o n tro l
B ia s C o n tro l
LC D C O M M O N C ontrol
L C D S E G M E N T C o n tro l
DC / DC
COM
SEG
Fig. 11 LCD Driver Control Block
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 25
EM78862C
8-Bit RISC Type Microprocessor COM Signal: The number of COM pins varies according to the duty cycle in use as described in the next paragraph. SEG Signal: The 32 segment signal pins are connected to the corresponding display RAM Address 20h ~ 2Fh, 40h ~ 4Fh, A0h ~ AFh, and C0h to CFh. All data address from Com0 ~ Com7 (located within Adress 20h ~ 2Fh, 40h ~ 4Fh) and Com8 ~ Com15 (located within Address A0h ~ AFh and C0h ~ CFh) are needed.
Fig.12 LCD DC/DC and Bias Generator
FRAME V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND
dark
COM0
COM1
COM2
SEG
SEG light
V1 V2 V4 V5 GND
Fig.13 Relation Between Bias and V1 to V5
26 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
6.10 Code Options
The EM78862C IC has a built-in CODE option register that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution.
Bit 0
OSCSEL
Bit 0 (OSCSEL): Oscillator option 0: RC mode 1: Crystal mode RC or crystal oscillator is selected by OSCSEL bit of code option.
6.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods). Unless the program counter is changed by instructions "MOV R2, A," "ADD R2, A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2, A," "BS(C) R2, 6," "CLR R2," etc.). Under this condition, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: a) Change one instruction cycle to consist of 4 oscillator periods. b) Execute within two instruction cycles, "JMP," "CALL," "RET," "RETL," & "RETI," or the conditional skip ("JBS," "JBC," "JZ," "JZA," "DJZ," & "DJZA") instructions which were tested to be true. Also execute within two instruction cycles the instructions that are written to the program counter. Furthermore, the instruction can provide the following features: Every bit of any register can be set, cleared, or tested directly. The I/O register can be regarded as a general register. That is, the same instruction can operate on the I/O register.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 27
EM78862C
8-Bit RISC Type Microprocessor
BINARY INSTRUCTION
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr
0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr
NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A R2+1 R2 , R2+A R2 Bits 8~9 of R2 unchanged AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR2 /R A /R ( R R+1 ( A R+1 ( R R-1 ( A, skip if zero R-1 ( R, skip if zero R(n) ( A(n-1), R(0) ( C, C ( A(7)
None C None T, P T, P None 1 None None None None None None 1 Z, C, DC None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C
28 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor 1. This instruction is applicable to IOC5 ~ IOC9, IOCA, IOCB, IOCC, IOCD, IOCE, & IOCF only. 2 Source and destination must be the same.
BINARY INSTRUCTION HEX MNEMONIC OPERATION STATUS AFFECTED
0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0010 1 1110 1000 kkkk 1 1111 kkkk kkkk
06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E02 1E8k 1Fkk
RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
R(n) ( R(n-1), R(0) ( C, C ( R(7) R(n) ( A(n+1), R(7) ( C, C ( A(0) R(n) ( R(n+1), R(7) ( C, C ( R(0) R(0-3) ( A(4-7), R(4-7) ( A(0-3) R(0-3) R(4-7) R+1 ( A, skip if zero R+1 ( R, skip if zero 0 ( R(b) 1 ( R(b) if R(b)=0, skip if R(b)=1, skip PC+1 ( [SP], (Page, k) ( PC (Page, k) ( PC k(A A(k(A A&k(A A(k(A k ( A, [Top of Stack] ( PC k-A ( A PC+ 1 [SP], 001H ( PC k->R5(3:0) k+A ( A
C C C None None None None None 3 None 4 None None None None None Z Z Z None Z, C, DC None None Z, C, DC
3. This instruction is not recommended for RF operation. 4. This instruction cannot operate under RF. The symbol "R" in the instruction set represents a register designation that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. The symbol "b" represents a bit field designator that selects the value for the bit that is located in the register "R" and affects operation. The symbol "k" represents an 8 or 10-bit constant or literal value.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 29
EM78862C
8-Bit RISC Type Microprocessor
7
Absolute Maximum Ratings
RATING SYMBOL VALUE UNIT
DC Supply Voltage Input Voltage Operating Temperature Range
Vdd Vin Ta
-0.3 to 5.5 Vdd 0.5 0 to 70
V V
8
DC Electrical Characteristics
Ta=0 ~ 70 , VDD=3V, VSS=0V
Parameter Condition Min Type Max 1 1 Unit A A
Symbol
IIL1 IIL2 VIH VIL VIHT VILT VIHX VILX VOH1
Input Leakage Current for input pins Input Leakage Current for bi-directional pins Input High Voltage Input Low Voltage Input High Threshold Voltage Input Low Threshold Voltage Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Port 8,9) (Port7) Output Low Voltage (Port 8,9) (Port 7)
VIN = VDD, VSS VIN = VDD, VSS RESET RESET OSCI OSCI IOH = -1.26mA IOH = -2.15mA IOL = IOL = 3.8mA 6.8mA
0.8VDD VSS 0.4VDD 0.7VDD 0.8VDD 0.8VDD VSS VSS -
-
VDD 0.2VDD 0.16VDD
V V V V V V V V V V V V
A A A
-
0.3VDD
-8 1 15
VDD VDD 0.2VDD 0.2VDD 1.5VDD 1.47VDD -12 4 25
VOL1
Vlcd IPH ISB1
LCD driver voltage Pull-high current Power down current (SLEEP mode)
Ilcd = 0 uA Ilcd = -150 uA Pull-high active input pin at VSS All input and I/O pin at VDD, output pin floating, WDT disabled. No load. All input and I/O pin at VDD, output pin are floating, WDT disabled, LCD disabled. No load. All input and I/O pin at VDD, output pin are floating, WDT disabled, LCD enabled. No load. CLK=32.768kHz, all input and I/O pin at VDD, output pin floating, WDT disabled, LCD enabled. No load. RESET=High, CLK=3.579MHz, output pin floating, LCD enabled. No load.
ISB2
Power down current (IDLE mode)
-
45
75
A
ISB3
Low clock current (GREEN mode) Operating supply current (NORMAL mode)
-
50
80
A
ICC
-
1.0
1.3
mA
30 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
9
AC Electrical Characteristics
Ta=0
Symbol
~ 70
, VDD=3V, VSS=0V
Conditions Min Type Max Unit
Parameter
Dclk Tins Tdrh Twdt
Input CLK duty cycle Instruction cycle time Device delay hold time Watchdog timer period Ta = 25C 32.768K 3.579M
45 -
50 60 550 16 16
55 -
%
s ns
ms ms
Description
Symbol
Min
Type
Max
Unit
OSC start up (32.768Hz) (3.579MHz PLL)
Tosc
--
440 16
ms
10 Timing Diagram
Fig. 14 AC Timing
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 31
EM78862C
8-Bit RISC Type Microprocessor
11 Application Circuit
11.1 Application with Crystal Mode
VDD
10Kohm
VDD
/RESET COM 0.1uF LCD Panel 32x16
PLLC 0.01uF
SEG/Port 8, 9
EM78862C
22PF OSCI
32.768kHz
Port 7
KEY PAD C45 C15 TEST GND C1A C1B
OSCO 22PF
1uF
1uF
1uF
Fig. 15. Application with Crystal Mode
32 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
11.2 Application with RC Mode
VDD
10K
VDD
/RESET COM 0.1 LCD Panel 32x16
PLLC 0.01
SEG/Port 8, 9
EM78862C
Port 7 2Mohms OSCI KEY PAD C45 OSCO C15 TEST GND C1A C1B
1
1
1
Fig. 16. Application with RC Mode
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 33
EM78862C
8-Bit RISC Type Microprocessor
12 Bonding Coordinates Subsidiary
12.1 Pad Configuration
Fig. 17 ePV6300 Pad Configuration
34 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
EM78862C
8-Bit RISC Type Microprocessor
12.2 Pad Name and Coordinates Table
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
* 35
EM78862C
8-Bit RISC Type Microprocessor
36 *
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)

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